1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, more particularly to a semiconductor memory having a serial access circuit.
2. Description of the Related Art
With the progress in memory technology, a semiconductor memory having a serial access function has been developed and put into practical application in place of a conventional random access memory in the field of image processing. Dual port memories, line memories and field memories are typical examples of the above mentioned memory having the serial access function. In the field of image processing which has made a remarkable progress in recent years, for example, the dual port memory is used as a memory (referred to as a "video memory") for holding image data. The dual-port memory of this kind includes a random access port and a serial access port on the single chip. The random access port is the same as the port provided to a conventional RAM (Random Access Memory). Through this port, one bit is read from or written into each arbitrarily accessed memory cell in the case of a 1-bit output type memory, while in the case of a memory for multi-bit parallel output type, the port is used to read or write a plurality of bits at a time. On the other hand, the serial access port usually has a buffer (hereinafter referred to as "line buffer") corresponding to the number of bits of one word, is used to simultaneously receive all the bits in the memory cells connected to the word line selected in accordance with row address information and output them serially to the outside.
In such a dual-port memory used as a video memory, the random access port and the serial access port can be used asynchronously so that the read/write of image data between CPU and the video memory and the readout of display data from the video memory to a display (such as a CRT or a liquid crystal display) can be made asynchronously. Therefore, the dual-port memory can greatly contribute to the improvement in processing efficiency of CPU, high speed display/simplification of display processing and digitallization of TV, VTR, and the like.
In the above dual port memory, the serial access port includes a word data latch circuit (hereinafter referred to as the "data register") for holding data derived from one selected word, a serial selection circuit for serially selecting data stored in the data register one by one, and a serial port for outputting data designated by the serial selection circuit.
In the above serial access port, data read out on the respective bit lines are transferred to the data register via transfer gates in parallel during a data transfer cycle. During this data transfer cycle, the operation of the serial selection circuit must be interrupted. Therefore, data length which can be read out continuously without interruption is limited to the bit number of the respective word lines. In this connection, it is theoretically possible to avoid the above interruption due to the data transfer cycle by making the data transfer cycle very short and causing the shortened data transfer cycle within the period between the two adjacent serial read operations of the serial selection circuit. However, this method requires to control the operations of the transfer gates and the serial selection circuit with high accuracy. Thus, this method is not practical.
Under the above circumstances, it has been proposed such technique that the data register and transfer gates are splitted into first and second sections, respectively. When bit storages of the first section of data register are sequentially accessed by the serial selection circuit, the second section of the transfer gates are enabled to transfer data on half the bit lines to the second section of the data register. Similarly, when bit storages of the second section of the data register are sequentially accessed by the serial selection circuit, the first section of the transfer gates are enabled to transfer data on the other half the bit lines to the first section of the data register in parallel. Thus, data over a plurality of row addresses i.e., word lines can be read out consecutively without interruption due to the data transfer cycle by alternately controlling the first and second sections of data registers and transfer gates in interleaved manner.
However, according to this method, data on the half of the bit lines and data on the other half of the bit lines must be read out alternately and it is impossible to read data on the half of the bit lines and at a first row address and data on the same half of the bit lines and at a second row address continuously without interruption.